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1 ltc1283 3v single chip 10-bit data acquisition system d u escriptio s f ea t u re n single supply 3.3v or 3.3v operation n software programmable features: unipolar/bipolar conversions 4 differential/8 single-ended inputs msb- or lsb-first data sequence variable data word length n built-in sample-and-hold n direct 4-wire interface to most mpu serial ports and all mpu parallel ports n 15khz maximum throughput rate u a o pp l ic at i ty p i ca l linearity plot key specificatio s u n minimum guaranteed supply voltage: 3v n resolution: 10 bits n offset error: 0.5lsb max n linearity error: 0.5lsb max n gain error (ltc1283a): 1lsb max n conversion time: 44 m s n supply current: 350 m a max, 150 m a typ output code 0 error (lsbs) 0 0.5 1024 ltc1283 ?ta02 0.5 1.0 512 1.0 the ltc1283 is a 3v data acquisition component which contains a serial i/o successive approximation a/d con- verter. it uses ltcmos tm switched capacitor technology to perform either 10-bit unipolar, or 9-bit plus sign bipolar a/d conversions. the 8-channel input multiplexer can be configured for either single-ended or differential inputs (or combinations thereof). an on-chip sample-and-hold is included for all single-ended input channels. the serial i/o is designed to be compatible with industry- standard full-duplex serial interfaces. it allows either msb- or lsb-first data and automatically provides 2s comple- ment output coding in the bipolar mode. the output data word can be programmed for a length of 8-, 10-, 12-, or 16-bit. this allows easy interface to shift registers and a variety of processors. both the ltc1283a and ltc1283 are specified with offset and linearity errors less than 0.5lsb. the ltc1283a has a gain error limit of 1lsb. the 1283 is specified with a gain error limit of 2lsb for applications where gain is adjustable or less critcial. ltcmos is a trademark of linear technology corp. differential input ltc1283 3v bipolar input ?v 3v t ?v unipolar inputs (+) (? unipolar input mpu (e.g., 83cl410) p1.1 p1.2 p1.3 p1.4 serial data link for 83cl410 code see applications information section ltc1283 ?ta01 d out d in sclk cs 4.7 m f 3v
2 ltc1283 a u g w a w u w a r b s o lu t exi t i s symbol parameter conditions min typ max units v cc positive supply voltage v C = 0v 3.0 3.6 v v C negative supply voltage v cc = 3.3v C 3.6 0 v f sclk shift clock frequency v cc = 3v 0 500 khz f aclk a/d clock frequency v cc = 3v t a 25 c 0.01 1.00 mhz t a 70 c 0.05 1.00 mhz t cyc total cycle time see operating sequence 10 sclk + cycles 48 aclk t hcs hold time, cs low after last sclk v cc = 3v 0 ns t hdi hold time, d in after sclk - v cc = 3v 200 ns t sucs setup time cs before clocking in first address bit (note 8) v cc = 3v 2 aclk cycles + 1 m s t sudi setup time, d in stable before sclk - v cc = 3v 400 ns t whaclk aclk high time v cc = 3v 250 ns t wlaclk aclk low time v cc = 3v 400 ns t whcs cs high time during conversion v cc = 3v 44 aclk cycles ltc1283/ltc1283a supply voltage (v cc ) to gnd or v C ......................... 12v voltage analog and reference inputs ................................. (v C ) C0.3v to v cc + 0.3v digital inputs ......................................... C0.3v to 12v digital outputs ........................... C0.3v to v cc + 0.3v (notes 1 and 2) negative supply voltage (vC) ..................... C6v to gnd power dissipation .............................................. 500mw operating temperature LTC1283AC, ltc1283c ......................... 0 c to 70 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c reco e ded operati g co ditio s w u w u u u wu u package / o rder i for atio order part number LTC1283ACn ltc1283cn order part number LTC1283ACs ltc1283cs 1 2 3 4 5 6 7 8 9 10 top view n package 20-lead plastic dip 20 19 18 17 16 15 14 13 12 11 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd v cc aclk sclk d in d out cs ref + ref v ? agnd t j max = 150 c, q ja = 100 c/w 1 2 3 4 5 6 7 8 9 10 top view s package 20-lead plastic sol 20 19 18 17 16 15 14 13 12 11 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd v cc aclk sclk d in d out cs ref + ref v agnd t j max = 150 c, q ja = 130 c/w consult factory for industrial and military grade parts
3 ltc1283 ltc1283a ltc1283 parameter conditions min typ max min typ max units offset error (note 4) l 0.5 0.5 lsb linearity error (notes 4 and 5) l 0.5 0.5 lsb gain error (note 4) l 1.0 2.0 lsb minimum resolution for which no l 10 10 bits missing codes are guaranteed reference input resistance 10 10 k w analog and ref input range (note 6) v on channel leakage current on channel = 3v l 11 m a (note 7) off channel = 0v on channel = 0v l C1 C1 m a off channel = 3v off channel leakage current on channel = 3v l C1 C1 m a (note 7) off channel = 0v on channel = 0v l 11 m a off channel = 3v (v C ) C 0.05v to v cc + 0.05v ac characteristics co verter a d ultiplexer characteristics uu w (note 3) (note 3) e lectr ic al c c hara ter st ics digital a d u i dc symbol parameter conditions min typ max units t acc delay time from cs to d out data valid (note 8) 2 aclk cycles t smpl analog input sample time see operating sequence 5 sclk cycles t conv conversion time see operating sequence 44 aclk cycles t ddo delay time, sclk to d out data valid see test circuts l 400 900 ns t dis delay time, cs - to d out hi-z see test circuits l 240 500 ns t en delay time, 2nd clk to d out enabled see test circuits l 300 800 ns t hdo time output data remains valid after sclk 75 ns t f d out fall time see test circuits l 90 300 ns t r d out rise time see test circuits l 80 300 ns c in input capacitance analog inputs on channel 65 pf off channel 5 pf digital inputs 5 pf ltc1283/ltc1283a symbol parameter conditions min typ max units v ih high level input voltage v cc = 3.6v l 1.7 v v il low level input voltage v cc = 3v l 0.45 v i ih high level input current v in = v cc l 2.5 m a i il low level input current v in = 0v l C 2.5 m a v oh high level output voltage v cc = 3v, i o = C 20 m a 2.6 2.8 v i o = C 200 m a l 2.0 v v ol low level output voltage v cc = 3v, i o = 20 m a 0.05 v i o = 400 m a l 0.10 0.30 v ltc1283/ltc1283a (note 3)
4 ltc1283 e lectr ic al c c hara ter st ics digital a d u i dc symbol parameter conditions min typ max units i oz hi-z output leakage v out = v cc , cs high l 3 m a v out = 0v, cs high l C3 m a i source output source current v out = 0v C 4.5 ma i sink output sink current v out = v cc 4.5 ma i cc positive supply current cs high, ref + open l 150 350 m a i ref reference current v ref = 2.5v l 250 500 m a i C negative supply current cs high, v C = C 3v l C1 C 50 m a ltc1283/ltc1283a (note 3) the l denotes specifications which apply over the operating temperature range; all other limits and typicals t a = 25 c. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to ground with dgnd, agnd and ref C wired together (unless otherwise noted). note 3: v cc = 3v, v ref + = 2.5v, v ref C = 0v, v C = 0v for unipolar mode and C 3v for bipolar mode, aclk = 1mhz, sclk = 0.25mhz unless otherwise specified. note 4: these specifications apply for both unipolar and bipolar modes. in bipolar mode, one lsb is equal to the bipolar input span (2v ref ) divided by 1024. for example, when v ref = 2.5v, 1lsb (bipolar) = 2(2.5v)/1024 = 4.88mv. note 5: linearity error is the deviation from ideal of the slope between the two end points of the transfer curve. note 6: two on-chip diodes are tied to each reference and analog input which will conduct for reference or analog input voltages one diode drop below v C or one diode drop above v cc . be careful during testing at low v cc levels, as high level reference or analog inputs can cause this input diode to conduct, especially at elevated temperatures, and cause errors for inputs near full scale. this spec allows 50mv forward bias of either diode. this means that as long as the reference or analog input does not exceed the supply voltage by more than 50mv, the output code will be correct. note 7: channel leakage current is measured after the channel selection. note 8: to minimize errors caused by noise at the chip select input, the internal circuitry waits for two aclk falling edges after a chip select falling edge is detected before responding to control input signals. therefore, no attempt should be made to clock an address in or data out until the minimum chip select setup time has elapsed. cc hara terist ics uw a t y p i ca lper f o r c e supply current vs temperature reference current vs temperature ambient temperature (?) ?0 0 supply current, i cc ( m a) 100 250 0 50 75 ltc1283 ?g01 50 200 150 ?5 25 100 125 ref + open aclk = 500khz v cc = cs = 3v reference voltage (v) 0 6 8 10 2.0 ltc1283 ?g03 4 2 0 0.5 1.0 1.5 2.5 5 7 9 3 1 v cc = 3v aclk = 500khz offset error (lsbs = 1 1024 v ref ) unadjusted offset error vs reference voltage temperature (?) ?0 0 i ref ( m a) 200 500 0 50 75 ltc1283 ?g02 100 400 300 ?5 25 100 125 v cc = 3v v ref = 2.5v
5 ltc1283 cc hara terist ics uw a t y p i ca lper f o r c e linearity error vs reference voltage change in linearity error vs temperature maximum conversion clock rate vs temperature change in gain error vs temperature maximum conversion clock rate vs source resistance maximum conversion clock rate vs reference voltage change in full-scale error vs reference voltage change in offset error vs temperature ambient temperature (?c) ?0 maximum aclk frequency* (mhz) 1.75 25 ltc1283 ?g09 1.0 0.5 ?5 0 50 0.25 0 2.0 1.5 1.25 0.75 75 100 125 v cc = 3v v ref = 2.5v r source (k w ) 1 0 maximum aclk frequency* (khz) 250 500 750 1000 1500 10 100 ltc1283 ?g11 1250 v cc = 3v + input ?input r source v in reference voltage (v) 0 change in gain error (lsb) 0.6 0.8 1.0 2.0 ltc1283 ?g04 0.4 0.2 0 0.5 1.0 1.5 2.5 0.5 0.7 0.9 0.3 0.1 v cc = 3v aclk = 500khz reference voltage (v) 0 0.6 0.8 1.0 2.0 ltc1283 ?g05 0.4 0.2 0 0.5 1.0 1.5 2.5 0.5 0.7 0.9 0.3 0.1 v cc = 3v aclk = 500khz linearity error (lsbs = 1 1024 v ref ) ambient temperature (?) ?0 0 magnitude of offset change, ?d offset ? (lsb) 0.2 0.5 0 50 75 ltc1283 ?g06 0.1 0.4 0.3 ?5 25 100 125 v cc = 3v v ref = 2.5v aclk = 500khz ambient temperature (?) ?0 0 magnitude of linearity change, ?d linearity ? (lsb) 0.2 0.5 0 50 75 ltc1283 ?g07 0.1 0.4 0.3 ?5 25 100 125 v cc = 3v v ref = 2.5v aclk = 500khz temperature (?) ?0 0 magnitude of gain change, ?d gain ? (lsb) 0.2 0.5 0 50 75 ltc1283 ?g08 0.1 0.4 0.3 ?5 25 100 125 v cc = 3v v ref = 2.5v aclk = 500khz reference voltage (v) 0 0 maximum aclk frequency* (khz) 250 500 750 1000 1250 1500 0.5 1.0 1.5 2.0 ltc1283 ?g10 2.5 v cc = 3v *maximum aclk frequency represents the aclk frequency at which a 0.1lsb shift in the error at any code transition from its 100khz value is first detected. **maximum r filter represents the filter resistor value at which a 0.1lsb change in full-scale error from its value at r filter = 0 is first detected. maximum filter resistor vs cycle time cycle time ( m s) 100 maximum r filter ** ( w ) 1k 10k 100k 10 1000 10000 ltc1283 ?g12 10 100 + ? v in r filter c filter 3 1 m f v cc = 3v
6 ltc1283 cc hara terist ics uw a t y p i ca lper f o r c e sample-and-hold acquisition time vs source resistance input channel leakage current vs temperature noise error vs reference voltage reference voltage (v) 0 0 peak-to-peak noise error (lsb ) 0.2 0.4 0.6 0.8 1.0 1.2 0.5 1.0 1.5 2.0 ltc1283 ?g15 2.5 v cc = 3v aclk = 500khz ltc1283 noise = 200 m v p-p ambient temperature (?) ?0 0.01 input channel leakage current (na) 0.1 1 10 100 25 0 25 50 ltc1283 ?g14 75 100 125 v cc = 3v v ref = 2.5v on channel off channel 1000 guaranteed pi fu ctio s u uu # pin function description 1-8 ch0-ch7 analog inputs the analog inputs must be free of noise with respect to agnd. 9 com common the common pin defines the zero reference point for all single-ended inputs. it must be free of noise and is usually tied to the analog ground plane. 10 dgnd digital ground this is the ground for the internal logic. tie to the ground plane. 11 agnd analog ground agnd should be tied directly to the analog ground plane. 12 v C negative supply tie v C to most negative potential in the circuit. (ground in single supply applications.) 13, 14 ref C , ref + reference inputs the reference inputs must be kept free of noise with respect to agnd. 15 cs chip select input a logic low on this input enables data transfer. 16 d out digital data output the a/d conversion result is shifted out of this output. 17 d in data input the a/d configuration word is shifted into this input. 18 sclk shift clock this clock synchronizes the serial data transfer. 19 aclk a/d conversion clock this clock controls the a/d conversion process. 20 v cc positive supply this supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. w i dagra b l o c k r source (k w ) 0.1 1 s&h acquisition time to 0.1% ( m s) 10 110 ltc1283 ?g13 5 v cc = 3v v ref = 2.5v t a = 25? 0v to 2.5v input step + ? v in r source + 9 8 7 6 4 3 2 input shift register sample- and- hold 10-bit capacitive dac v cc 20 analog input mux 1 2 3 4 5 6 7 8 9 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com d out 16 sclk 18 control and timing 15 cs ltc1283 bd 17 ref + 14 dgnd 10 agnd 11 v 12 ref 13 comp output shift register d in 19 aclk 10-bit sar
7 ltc1283 test circuits 3v a a i off i on polarity off channels on channel ltc1283 tc01 on and off channel leakage current sclk d out 0.6v t ddo 0.6v 2.0v ltc1283 tc02 voltage waveforms for d out delay time, t ddo d out 0.6v 2.0v t r t f ltc1283 tc03 voltage waveform for d out rise and fall times, t r and t f d out 1.5v 3k 100pf test point ltc1283 tc06 load circuit for t ddo , t r , t f and t en d out 3k 100pf test point 3v waveform 2 waveform 1 ltc1283 tc05 load circuit for t dis d out waveform 1 (see note 1) t dis 90% 10% d out waveform 2 (see note 2) cs note 1: waveform 1 is for an output with internal conditions such that the output is high unless disabled by the output control. note 2: waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control. ltc1283 tc04 t en 2.0v 0.6v aclk 12 2.0v voltage waveforms for t en and t dis
8 ltc1283 u s a o pp l ic at i wu u i for atio the ltc1283 is a 3v data acquisition component which contains the following functional blocks: 1. 10-bit successive approximation capacitive a/d converter 2. analog multiplexer (mux) 3. sample-and-hold (s&h) 4. synchronous, full duplex serial interface 5. control and timing logic digital considerations 1. serial interface the ltc1283 communicates with microprocessors and other external circuitry via a synchronous, full duplex, 4- wire serial interface (see operating sequence). the shift clock (sclk) synchronizes the data transfer with each bit being transmitted on the falling sclk edge and captured on the rising sclk edge in both transmitting and receiving systems. the data is transmitted and received simulta- neously (full duplex). data transfer is initiated by a falling chip select (cs) signal. after the falling cs is recognized, an 8-bit input word is shifted into the d in input which configures the ltc1283 for the next conversion. simultaneously, the result of the previous conversion is output on the d out line. at the end of the data exchange the requested conversion begins and cs should be brought high. after t conv , the conver- sion is complete and the results will be available on the next data transfer cycle. as shown below, the result of a conversion is delayed by one cs cycle from the input word requesting it. 2. input data word the ltc1283 8-bit input data word is clocked into the d in input on the first eight rising sclk edges after chip select is recognized. further inputs on the d in pin are then ignored until the next cs cycle. the eight bits of the input word are defined as follows: d in d out d out word 0 d in word 1 data transfer d out word 2 d in word 3 d out word 1 d in word 2 data transfer t conv a/d conversion t conv a/d conversion ltc1283 ?ai02 operating sequence (example: differential inputs (ch3-ch2), bipolar, msb-first and 10-bit word length) sgl/ diff select 1 select 0 uni msbf wl1 mux address msb-first/ lsb-first unipolar/ bipolar word length ltc1283 ?ai03 odd/ sign wl0 data input (d in ) word: 1 2345678910 b9 (sb) b8 b7 b6 b5 b4 b3 b2 b1 b0 sclk d in d out cs ltc1283 ?ai01 sgl/ diff odd/ sign t conv t smpl t cyc don? care don? care sel 1 sel 0 uni msbf wl1 wl0 shift configuration word in shift a/d result out and new configuration word in
9 ltc1283 u s a o pp l ic at i wu u i for atio multiplexer (mux) address the first four bits of the input word assign the mux configuration for the requested conversion. for a given channel selection, the converter will measure the voltage between the two channels indicted by the + and C signs in the selected row of table 1. note that in differential mode (sgl/diff = 0) measurements are limited to four adjacent input pairs with either polarity. in single-ended mode, all input channels are measured with respect to com. figure 1 shows some examples of multiplexer assignments. 0 1 2 3 4 5 6 7 channel com ( ) 8 single-ended + + + + + + + 0,1 channel 4 differential 2,3 4,5 6,7 + ( ) + + ( ) + ( ) + ( ) ( + ) ( + ) ( + ) ( + ) 4 5 6 7 channel com ( ) combinations of differential and single-ended + + + + + + 0,1 2,3 com (unused) changing the mux assignment ?n the fly com ( ) 4,5 6,7 5,4 1st conversion 2nd conversion + + + + + 7 6 { { { { { { { { { { ltc1283 ?f01 figure 1. examples of multiplexer options on the ltc1283 sgl/ diff 0 0 0 0 0 0 0 0 0dd/ sign 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 select 0 0 1 0 1 0 1 0 1 0 + 7 ? + 1 ? + 2 + 3 ? + 4 + 5 ? + 6 + mux address differential channel selection sgl/ diff 1 1 1 1 1 1 1 1 0dd/ sign 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 select 0 0 1 0 1 0 1 0 1 0 + 7 + 1 + 2 + 3 + 4 + 5 + 6 + mux address single-ended channel selection com ? table 1. multiplexer channel selection
10 ltc1283 unipolar/bipolar (uni) the fifth input bit (uni) determines whether the conver- sion will be unipolar or bipolar. when uni is a logical one, a unipolar conversion will be performed on the selected u s a o pp l ic at i wu u i for atio input voltage. when uni is a logical zero, a bipolar conver- sion will result. the input span and code assignment for each conversion type are shown in the figures below. bipolar transfer curve (uni = 0) 1lsb v ref ?2lsb v ref ?1lsb v ref v in 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 ?lsb ?lsb ? ref ? ref + 1lsb ltc1283 ai05 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 ? ? ? 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 ?lsb ?lsb ? ? ? ?v ref ) + 1lsb ?v ref ) 0.0049v 0.0098v ? ? ? 2.4951v 2.5000v output code 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 ? ? ? 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 input voltage v ref ?1lsb v ref ?2lsb ? ? ? 1lsb 0v input voltage (v ref = 2.5v) 2.4951v 2.4902v ? ? ? 0.0049v 0v ltc1283 ai07 bipolar output code (uni = 0) unipolar transfer curve (uni = 1) 0v 1lsb v ref ?2lsb v ref ?1lsb v ref v in 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 ? ? ltc1283 ai04 unipolar output code (uni = 1) output code 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 ? ? ? 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 input voltage v ref ?1lsb v ref ?2lsb ? ? ? 1lsb 0v input voltage (v ref = 2.5v) 2.4976v 2.4951v ? ? ? 0.0024v 0v ltc1283 ai06
11 ltc1283 1 aclk cycle. after a change of state on the cs input, the ltc1283 waits for two falling edges of the aclk before recognizing a valid chip select. one indication of cs low recognition is the d out line becoming active (leaving the hi-z state). note that the deglitching applies to both the rising and falling cs edges. msb-first/lsb-first format (msbf) the output data of the ltc1283 is programmed for msb- first or lsb-first sequence using the msbf bit. for msb- first output data the input word clocked to the ltc1283 should always contain a logical one in the sixth bit location (msbf bit). likewise for lsb-first output data, the input word clocked to the ltc1283 should always contain a zero in the msbf bit location. the msbf bit in a given d in word will control the order of the next d out word. the msbf bit affects only the order of the output data word. the order of the input word is unaffected by this bit. u s a o pp l ic at i wu u i for atio msbf 0 1 output format lsb-first msb-first ltc1283 ai08 figure 2 shows how the data output (d out ) timing can be controlled with word length selection and msb/lsb-first format selection. 3. deglitcher a deglitching circuit has been added to the chip select input of the ltc1283 to minimize the effects of errors caused by noise on that input. this circuit ignores changes in state on the cs input that are shorter in duration than 4. cs low during conversion in the normal mode of operation, cs is brought high during the conversion time (see figure 3). the serial port ignores any sclk activity while cs is high. the ltc1283 will also operate with cs low during the conversion. in this mode, sclk must remain low during the conversion as shown in figure 4. after the conversion is complete, the d out line will become active with the first output bit. then the data transfer can begin as normal. 5. microprocessor interfaces the ltc1283 can interface directly (without external hard- ware) to most popular microprocessor (mpu) synchro- nous serial formats (see table 2). if an mpu without a serial interface is used, then four of the mpus parallel port lines can be programmed to form the serial link to the ltc1283. included here are three serial interface ex- amples and one example showing a parallel port pro- grammed to form the serial interface. word length (wl1, wl0) the last two bits of the input word (wl1 and wl0) program the output data word length of the ltc1283. word lengths of 8-, 10-, 12- or 16-bit can be selected according to the following table. the wl1 and wl0 bits in a given d in word control the length of the present, not the next, d out word. wl1 and wl2 are never dont cares and must be set for the correct d out word length even when a dummy d in word is sent. on any transfer cycle, the word length should be made equal to the number of sclk cycles sent by the mpu. wl1 0 0 1 1 output word length 8 bits 10 bits 12 bits 16 bits ltc1283 ?ai09 wl0 0 1 0 1 cs aclk d out hi-z valid output cs aclk d out valid output ltc1283 ?ai10 hi-z low cs recoginzed internally high cs recognized internally
12 ltc1283 u s a o pp l ic at i wu u i for atio figure 2. data output (d out ) timing with different word lengths t smpl b9 1 t conv b8 b7 b6 b5 b2 (sb) 8-bit word length sclk cs d out lsb-first t smpl b9 1 t conv (sb) 12-bit word length sclk cs d out lsb-first 10 12 d out msb-first d out msb-first (sb) t smpl 1 t conv 16-bit word length 10 16 fill zeroes * * in unipolar mode, these bits are filled with zeroes. in bipolar mode, the sign bit is extended into these locations. ltc1283 ?f02 b4 b3 b0 b1 b2 b3 b4 b7 b5 b6 b8 b7 b6 b5 b4 b3 b2 b1 b0 fill zeroes b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 * * sclk cs d out lsb-first d out msb-first b9 (sb) (sb) b8 b7 b6 b5 b4 b3 b2 b1 b0 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 the last two bits are truncated t smpl b9 1 t conv b8 b7 b6 b5 b2 (sb) 10-bit word length sclk cs d out lsb-first d out msb-first b4 b3 b0 b1 b2 b3 b4 b7 b5 b6 10 8 b1 b0 b8 b9 (sb) *****
13 ltc1283 u s a o pp l ic at i wu u i for atio figure 3. cs high during conversion figure 4. cs low during conversion serial port microprocessors most synchronous serial formats contain a shift clock (sclk) and two data lines, one for transmitting and one for receiving. in most cases data bits are transmitted on the falling edge of the clock (sclk) and captured on the rising edge. however, serial port formats vary among mpu manufacturers as to the smallest number of bits that can be sent in one group (e.g., 4-bit, 8-bit or 16-bit transfers). they also vary as to the order in which the bits are transmitted (lsb- or msb-first). the following examples show how the ltc1283 accommodates these differences. national microwire (cop820c) the cop820c transfers data msb-first and in 8-bit incre- ments. this is easily accommodated by setting the ltc1283 to msb-first format and 10-bit word length. the data output word is then received by the cop820c in one 8-bit block and one 2-bit block. table 2. 3v microprocessor with hardware serial interfaces compatible with the ltc1283* part number type of interface motorola mc68hc11 spi mc68hc05 spi rca cdp68hc05 spi national semiconductor cop800 family microwire/plus ? hpc16000 family microwire/plus ? texas instruments tms70c02 serial port tms70c42 serial port *contact factory for interface information for processors not on this list ? microwire/plus is a trademark of national semiconductor corp. b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 shift result out and new address in sclk cs d out d in t smpl sample analog input shift mux address in ltc1283 ?f03 40 to 44 aclk cycles odd/ sign sel 1 sel 0 uni msbf wl1 wl0 don? care sgl/ diff odd/ sign sel 1 sel 0 uni msbf wl1 wl0 sgl/ diff b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 shift result out and new address in sclk cs d out d in t smpl sample analog input shift mux address in ltc1283 ?f04 40 to 44 aclk cycles odd/ sign sel 1 sel 0 uni msbf wl1 wl0 don? care sgl/ diff odd/ sign sel 1 sel 0 uni msbf wl1 wl0 sgl/ diff sclk must remain low
14 ltc1283 u s a o pp l ic at i wu u i for atio cs sclk d in d out g1 sk so si analog inputs ltc1283 cop820c ltc1283 ?ai11 ? ? ? motorola spi (mc68hc05c4, mc68hc11) the mc68hc05c4 and mc68hc11 transfer data msb- first and in 8-bit increments. programming the ltc1283 for msb-first format and 16-bit word length allows the 10- bit data output to be received by the mpu as two 8-bit bytes with the final 6 unused bits filled with zeroes by the ltc1283. b9 b8 b7 b6 b5 b4 b3 b2 msb* lsb *b9 is msb in unipolar or sign bit in bipolar byte 1 ltc1283 ?ai14 b1 b0 0 0 0 0 0 0 byte 2 location a location a + 1 mnemonic comments bclr n c0 is cleared (cs goes low) lda load d in for ltc1283 into acc sta load d in from acc to spi data reg. start sck - nop 8 nops for timing lda load contents of spi status reg. into acc lda load ltc1283 d out from spi data reg. into acc (byte 1) sta load ltc1283 d out into ram (location a) mnemonic comments sta start next spi cycle - nop 6 nops for timing bset n co is set (cs goes high) lda load contents of spi status reg. into acc lda load ltc1283 d out from spi data reg. int acc (byte 2) sta load ltc1283 into ram (location a +1) hardware and software interface to motorola mc68hc05c4 and mc68hc11 processors d out from ltc1283 stored in mc68hc05c4 or mc68hc11 ram 98765432 msb* lsb *b9 is msb in unipolar or sign bit in bipolar byte 1 ltc1283 ?ai12 10xxxxxx byte 2 hardware and software interface to national semiconductor cop820c processor d out from ltc1283 stored in cop820c ram mnemonic comments ld (f0) ? 0d load 0d into f0 (d in ) ld (d5) ? 32 configure port g ld (ee) ? 8 configure control reg. ld (b) ? d4 port g data reg. into b ld (a) ? (f0) load d in into acc rbit 1 g1 reset (cs goes low) x (a) ?? (e9) load d in into shift reg. ld (b) ? ef load psw reg. addr in b sbit 2 transfer begins - nop 15 nops for timing mnemonic comments x(a) ?? (e9) load d out into acc sbit 2 transfer continues x (a) ?? (f3) load d out in addr f3 rbit 2 stop transfer ld (b) ? d4 put port g addr in b sbit 1 g1 set (cs goes high) x (a) ?? (e9) load d out into acc rc clear carry rrca shift right thru carry rrca shift right thru carry rrca shift right thru carry x (a) ?? (f4) load d out in addr f4 cs sclk d in d out c0 sck mosi miso analog inputs ltc1283 mc68hc05c4 mc68hc11 ltc1283 ?ai13 ? ? ?
15 ltc1283 u s a o pp l ic at i wu u i for atio hardware and software interface to ti tms70c42 processor texas instruments tms70c42 the tms70c42 transfers serial data in 8-bit increments, lsb-first. to accommodate this, the ltc1283 is pro- grammed for 16-bit word length and lsb-first format. the 10-bit output data is received by the processor as two 8-bit bytes, lsb-first. the ltc1283 fills the final 6 unused bits (after the msb) with zeroes. d out from ltc1283 stored in tms70c42 ram label mnemonic description start dint disables all interrupts movp % > 2a, p0 disable interrupt flags movp % > 02, p16 disable interrupt flags mov % > 60, b address of stack ldsp put address into pointer movp % > df, p5 configure port a movp % > 08, p6 enable tx by setting b3 = 1 movp % > 40, p21 reset the serial port movp % > 0c, p20 configure the serial port movp % > 00, p24 turn start bit off movp % > 00, p21 enable the serial port movp % > 00, p23 set sclk rate (timer 3) movp % > c0, p24 start timer loop mov % > df, a load d in word in a call sxtnbit routine that shifts data mov b, r5 put first 8 lsbs in r5 mov a, r6 put msbs in r6 sxtnbit andp % > fe, p4 a0 cleared (cs goes low) movp a, p26 put d in into txbuf label mnemonic description movp % > 40, p24 sclk off (timer 3 disabled) movp % > 17, p21 enable serial port movp % > c0, p24 sclk on (transfer begins) movp % > 16, p21 txen goes low mov % > 02, a load counter wait1 djnz a, wait1 loop while shift occurs nop delay movp p25, b put d out in b movp a, p26 load txbuf movp % > 40, p24 sclk off (timer 3 disable) movp % > 17, p21 enable serial port movp % > c0, p24 sclk on (transfer begins) movp % > 16, p21 txen goes low mov % > 02, a load counter wait2 djnz a, wait2 loop while shift occurs nop delay movp p25, a put d out in a orp % > 01, p4 a0 set (cs goes high) rets return to main program signetics 83cl410 to interface to the 83cl410, (a 3v version of the 80c51) the ltc1283 is programmed for msb-first format and 10- bit word length. the 83cl410 generates cs, sclk and d in on three port lines and reads d out on the fourth. parallel port microprocessors when interfacing the ltc1283 to an mpu which has a parallel port, the serial signals are created on the port with software. three mpu port lines are programmed to create the cs, sclk and d in signals for the ltc1283. a fourth port line reads the d out line. an example is made of the signetics 83cl410. hardware and software interface to signetics 83cl410 processor d out d in sclk cs aclk p1.1 p1.2 p1.3 p1.4 ale analog inputs ltc1283 83cl410 ltc1283 ?ai17 ? ? ? ? ? ? ? cs sclk d in d out ao sclk t xd r xd ltc1283 tms70c42 ltc1283 ?ai15 ? ? ? ? analog inputs 76543210 lsb fill with zeroes byte 1 ltc1283 ?ai16 00000098 byte 2 msb d out from ltc1283 stored in 83cl410 ram b9 b8 b7 b6 b5 b4 b3 b2 msb* lsb ltc1283 ?ai18 b1 b2 0 0 0 0 0 0 r2 r3 *b9 is msb in unipolar or sign bit in bipolar
16 ltc1283 6. sharing the serial interface the ltc1283 can share the same 3-wire serial interface with other peripheral components or other ltc1283s (see figure 5). in this case, the cs signals decide which ltc1283 is being addressed by the mpu. u s a o pp l ic at i wu u i for atio mnemonic description mov p1, #02h initialize port 1 (bit 1 is made an input) clr p1.3 sclk goes low setb p1.4 cs goes low continue: mov a, #0dh d in word for the ltc1283 is placed in acc clr p1.4 cs goes low mov r4, #08 load counter nop delay for deglitcher loop: mov c, p1.1 read data bit into carry rlc a rotate data bit into acc mov p1.2, c output d in bit to ltc1283 setb p1.3 sclk goes high clr p1.3 sclk goes low djnz r4, loop next bit mov r2, a store msbs in r2 mnemonic description mov c, p1.1 read data bit into carry clr a clear acc rlc a rotate data bit into acc setb p1.3 sclk goes high clr p1.3 sclk goes low mov c, p1.1 read data bit in carry rrc a rotate right into acc rrc a rotate right into acc mov r3, a store lsbs in r3 setb p1.3 sclk goes high clr p1.3 sclk goes low setb p1.4 cs goes high mov r5, #07h load counter delay: djnz r5, delay delay for ltc1283 to perform conversion ajmp continue repeat program 83cl410 code figure 5. several ltc1283s sharing one 3-wire serial interface analog considerations 1. grounding the ltc1283 should be used with an analog ground plane and single point grounding techniques. pin 11 (agnd) should be tied directly to this ground plane. pin 10 (dgnd) can also be tied directly to this ground plane because minimal digital noise is generated within the chip itself. pin 20 (v cc ) should be bypassed to the ground plane with a 4.7 m f tantalum with leads as short as possible. pin 12 (v C ) should be bypassed with a 0.1 m f ceramic disk. for single supply applications, v C can be tied to the ground plane. it is also recommended that pin 13 (ref C ) and pin 9 (com) be tied directly to the ground plane. all analog inputs should be referenced directly to the single point ground. digital inputs and outputs should be shielded from and/or routed away from the reference and analog circuitry. figure 6 shows an example of an ideal ground plane design for a two-sided board. of course this much ground plane will not always be possible, but users should strive to get as close to this ideal as possible. 2. bypassing for good performance, v cc must be free of noise and ripple. any changes in the v cc voltage with respect to analog ground during a conversion cycle can induce errors 8 channels 8 channels 8 channels 3 3 3 3 3-wire serial interface to other peripherals or ltc1283s 2 10 output port serial data mpu ltc1283 ?f05 ltc1283 cs ltc1283 cs ltc1283 cs
17 ltc1283 u s a o pp l ic at i wu u i for atio or noise in the output code. v cc noise and ripple can be kept below 1mv by bypassing the v cc pin directly to the analog ground plane with a 4.7 m f tantalum with leads as short as possible. figures 7 and 8 show the effects of good and poor v cc bypassing. 3. analog inputs because of the capacitive redistribution a/d conversion techniques used, the analog inputs of the ltc1283 have capacitive switching input current spikes. these current spikes settle quickly and do not cause a problem. however, if large source resistances are used or if slow settling op amps drive the inputs, care must be taken to insure that the transients caused by the current spikes settle completely before the conversion begins. source resistance the analog inputs of the ltc1283 look like 65pf capacitor (c in ) in series with a 500 w resistor (r on ) as shown in figure 9. c in gets switched between the selected + and C inputs once during each conversion cycle. large external source resistors and capacitances will slow the settling of the inputs. it is important that the overall rc time constants be short enough to allow the analog inputs to completely settle within the allowed time. figure 6. example ground plane for the ltc1283 vertical: 0.5mv/div horizontal: 10 m s/div figure 7. poor v cc bypassing. noise and ripple can cause a/d errors vertical: 0.5mv/div horizontal: 10 m s/div figure 8. good v cc bypassing keeps noise and ripple on v cc below 1mv 4th sclk r on = 500 w last sclk c in = 65pf ltc1283 ?? input r source + v in + c1 ? input r source v in c2 ltc1283 ?f09 figure 9. analog input equivalent circuit v 4.7 m f tantalum v cc ltc1283 ?f06 0.1 f ceramic disk analog ground plane 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
18 ltc1283 u s a o pp l ic at i wu u i for atio figure 10. + and C input settling windows + input settling this input capacitor is switched onto the + input during the sample phase (t smpl , see figure 10). the sample phase starts at the 4th sclk cycle and lasts until the falling edge of the last sclk (the 8th, 10th, 12th or 16th sclk cycle depending on the selected word length). the voltage on the + input must settle completely within this sample time. minimizing r source + and c1 will improve the input settling time. if large + input source resistance must be used, the sample time can be increased by using a slower sclk frequency or selecting a longer word length. with the minimum possible sample time of 8 m s, r source + < 2k and c1 < 20pf will provide adequate settling. C input settling at the end of the sample phase the input capacitor switches to the C input and the conversion starts (see figure 10). during the conversion, the + input voltage is effectively held by the sample-and-hold and will not affect the conversion result. however, it is critical that the C input voltage be free of noise and settle completely during the first four aclk cycles of the conversion time. minimizing r source C and c2 will improve settling time. if large C input source resistance must be used, the time allowed for settling can be extended by using a slower aclk fre- quency. at the maximum aclk rate of 1mhz, r source C < 1k and c2 < 20pf will provide adequate settling. vertical: 5mv/div horizontal: 1 m s/div figure 11. adequate settling of op amp driving analog input input op amps when driving the analog inputs with an op amp it is important that the op amp settle within the allowed time (see figure 10). again, the + and C input sampling times can be extended as described above to accommo- date slower op amps. most op amps including the lt1006 and lt1013 single supply op amps can be made to settle well even with the minimum settling windows of 8 m s (+ input) and 4 m s (C input) which occur at the maximum clock rates (aclk = 1mhz and sclk = 0.5mhz). figures 11 and 12 show examples of adequate and poor op amp settling. sclk cs ??input aclk ltc1283 ?f10 1234 ?? ?? ?? mux address shifted in t smpl last sclk (8th, 10th, 12th or 16th depending on word length) 1 234 1st bit test ?input must settle during this time sample hold ??input must settle during this time ?input ??
19 ltc1283 u s a o pp l ic at i wu u i for atio leakage specification of 1 m a (at 125 c) flowing through a source resistance of 1k will cause a voltage drop of 1mv or 0.4lsb. this error will be much reduced at lower temperatures because leakage drops rapidly (see typical curve of input channel leakage current vs temperature). noise coupling into inputs high source resistance input signals (>500 w ) are more sensitive to coupling from external sources. it is prefer- able to use channels near the center of the package (i.e., ch2-ch7) for signals which have the highest output resistance because they are essentially shielded by the pins of the package ends (dgnd and ch0). grounding any unused inputs (especially the end pin, ch0) will also reduce outside coupling into high source resistances. 4. sample-and-hold single-ended inputs the ltc1283 provides a built-in sample-and-hold (s&h) function for all signals acquired in the single-ended mode (com pin grounded). this sample-and-hold allows the ltc1283 to convert rapidly varying signals (see typical curve of s&h acquisition time vs source resistance). the input voltage is sampled during the t smpl time as shown in figure 10. the sampling interval begins after the fourth mux address bit is shifted in and continues during the remainder of the data transfer. on the falling edge of the final sclk, the s&h goes into hold mode and the conver- sion begins. the voltage will be held on either the 8th, 10th, 12th or 16th falling edge of the sclk depending on the word length selected. differential inputs with differential inputs, or when the com pin is not tied to ground, the a/d no longer converts just a single voltage but rather the difference between two voltages. in these cases, the voltage on the selected + input is still sampled and held and therefore may be rapidly time varying just as in single-ended mode. however, the voltage on the se- lected C input must remain constant and be free of noise and ripple throughout the conversion time. otherwise, the vertical: 5mv/div horizontal: 1 m s/div figure 12. poor op amp settling can cause a/d errors rc input filtering it is possible to filter the inputs with an rc network as shown in figure 13. for large values of c f (e.g., 1 m f), the capacitive input switching currents are averaged into a net dc current. therefore, a filter should be chosen with small resistor and large capacitor to prevent dc drops across the resistor. the magnitude of the dc current is approxi- mately i dc = 65pf v in /t cyc and is roughly proportional to v in . when running at the minimum cycle time of 68 m s, the input current equals 2.5 m a at v in = 2.5v. in this case, a filter resistor of 100 w will cause 0.1lsb of full-scale error. if a larger filter resistor must be used, errors can be eliminated by increasing the cycle time as shown in the typical curve maximum filter resistor vs cycle time. input leakage current input leakage currents can also create errors if the source resistance gets too large. for instance, the maximum input r filter v in c filter ltc1283 ?f13 ltc1283 ? i dc figure 13. rc input filtering
20 ltc1283 u s a o pp l ic at i wu u i for atio differencing operation may not be performed accurately. the conversion time is 44 aclk cycles. therefore, a change in the C input voltage during this interval can cause conversion errors. for a sinusoidal voltage on the C input this error would be: v error (max) = v peak 2 p f(C) 44/f aclk where f(C) is the frequency of the C input voltage, v peak is its peak amplitude and f aclk is the frequency of the aclk. in most cases v error will not be significant. for a 60hz signal on the C input to generate a 1/4lsb error (0.61mv) with the converter running at aclk = 1mhz, its peak value would have to be 38mv. 5. reference inputs the voltage between the reference inputs of the ltc1283 defines the voltage span of the a/d converter. the refer- ence inputs look primarily like a 10k resistor but will have transient capacitive switching currents due to the switched- capacitor conversion technique (see figure 14). during each bit test of the conversion (every 4 aclk cycles), a capacitive current spike will be generated on the reference pins by the a/d. these current spikes settle quickly and do not cause a problem. however, if slow settling circuitry is used to drive the reference inputs, care must be taken to insure that transients caused by these current spikes settle completely during each bit test of the conversion. show examples of both adequate and poor settling. using a slower aclk will allow more time for the refer- ence to settle. however, even at the maximum aclk rate of 1mhz most references and op amps can be made to settle within the 4 m s bit time. 3. it is recommended that the ref C input be tied directly to the analog ground plane. if ref C is biased at a voltage other than ground, the voltage must not change during a conversion cycle. this voltage must also be free of noise and ripple with respect to analog ground. r on 5pf to 30pf ltc1283 ref + r out v ref every 4 aclk cycles 14 13 ref ltc1283 ?f14 10k typ when driving the reference inputs, three things should be kept in mind: 1. the source resistance (r out ) driving the reference inputs should be low (less than 1 w ) to prevent dc drops caused by the 300 m a maximum reference current (i ref ). 2. transients on the reference inputs caused by the capaci- tive switching currents must settle completely during each bit test (each 4 aclk cycles). figures 15 and 16 figure 14. reference input equivalent circuit figure 15. adequate reference settling 6. reduced reference operation the effective resolution to the ltc1283 can be increased by reducing the input span of the converter. the ltc1283 exhibits good linearity and gain over a wide range of reference voltages (see typical curves of linearity and gain error vs reference voltage). however, care must be taken figure 16. poor reference settling can cause a/d errors horizontal: 1 m s/div vertical: 0.5mv/div vertical: 0.5mv/div horizontal: 1 m s/div
21 ltc1283 u s a o pp l ic at i wu u i for atio contribute virtually no uncertainty to the output code. however, for reduced references, the noise may become a significant fraction of an lsb and cause undesirable jitter in the output code. for example, with a 1v reference, this same 200 m v noise is 0.2lsb peak-to-peak. this will reduce the range of input voltages over which a stable output code can be achieved by 0.2lsb. if the reference is further reduced to 200mv, the 200 m v noise becomes equal to one lsb and a stable code may be difficult to achieve. in this case averag- ing readings may be necessary. this noise data was taken in a very clean setup. any setup induced noise (noise or ripple on v cc , v ref , v in or v C ) will add to the internal noise. the lower the reference voltage to be used, the more critical it becomes to have a clean, noise- free setup. when operating at low values of v ref because of the reduced lsb step size and the resulting higher accuracy requirement placed on the converter. the following factors must be considered when operating at low v ref values. 1. conversion speed (aclk frequency) 2. offset 3. noise conversion speed with reduced v ref with reduced reference voltages, the lsb step size is reduced and the ltc1283 internal comparator overdrive is reduced. with less overdrive, more time is required to perform a conversion. therefore, the maximum aclk frequency should be reduced when low values of v ref are used. this is shown in the typical curve of maximum conversion clock rate vs reference voltage. offset with reduced v ref the offset of the ltc1283 has a larger effect on the output code when the a/d is operated with reduced reference voltage. the offset (which is typically a fixed voltage) becomes a larger fraction of an lsb as the size of the lsb is reduced. the typical curve of unadjusted offset error vs reference voltage shows how offset in lsbs is related to reference voltage for a typical value of v os . for example, a v os of 0.5mv which is 0.2lsb with a 2.5v reference becomes 0.5lsb with a 1v reference and 2.5lsbs with a 0.2v reference. if this offset is unacceptable, it can be corrected digitally by the receiving system or by offsetting the C input to the ltc1283. noise with reduced v ref the total input referred noise of the ltc1283 can be reduced to approximately 200 m v peak-to-peak using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. this noise is insignificant with a 2.5v reference but will become a larger fraction of an lsb as the size of the lsb is reduced. the typical curve of noise error vs reference voltage shows the lsb contribution of this 200 m v of noise. for operation with a 2.5v reference, the 200 m v noise is only 0.08lsb peak-to-peak. in this case, the ltc1283 noise will a quick look circuit for the ltc1283 users can get a quick look at the function and timing of the ltc1283 by using the following simple circuit. ref + and d in are tied to v cc selecting a 3v input span, ch7 as a single-ended input, unipolar mode, msb-first format and 16-bit word length. aclk and sclk are tied together and driven by an external clock. cs is driven at 1/64 the clock rate by the cd4520 and d out outputs the data. all other pins are tied to a ground plane. the output data from the d out pin can be viewed on an oscilloscope which is set up to trigger on the falling edge of cs. scope trace of ltc1283 quick look circuit showing a/d output of 0101010101 (155 hex ) vertical: 1v/div, horizontal: 5 m s/div cs d out msb (b9) deglitcher time lsb (b0) fills zeroes
22 ltc1283 u s a o pp l ic at i ty p i ca l a quick look circuit for the ltc1283 sneak-a-bit is a trademark of linear technology corp. sneak-a-bit tm the ltc1283s unique ability to software select the polar- ity of the differential inputs and the output word length is used to achieve one more bit of resolution. using the circuit below with two conversions and some software, a 2s complement 10-bit + sign word is returned to memory inside the mpu. the mc68hc05c4 was chosen as an example; however, any processor could be used. two 10-bit unipolar conversions are performed: the first over a 0v to 3v span and the second over a 0v to C 3v span (by reversing the polarity of the inputs). the sign of the input is determined by which of the two spans contain it. then the resulting number (ranging from C 1023 to 1023 decimal) is converted to 2s complement notation and stored in ram. sneak-a-bit code ltc1283 ?ta05 mc68hc05c4 sck mosi miso co ?v 0.1 m f 1mhz clock other channels or sneak-a-bit inputs 3v ltc1283 cho ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd v cc aclk sclk d in d out cs ref + ref v agnd 10 m f v in 3v to 3v sneak-a-bit circuit d out from ltc1283 in mc68hc05c4 b10 b9 b8 b7 b6 b5 b4 b3 sign lsb ltc1283 ?ta07 b2 b1 b0 filled with 0? location $77 location $87 d in words for ltc1283 00111111 uni ltc1283 ?ta08 d in 1 msbf word length (odd/sign) mux addr. 01111111 d in 2 00111111 d in 3 ltc1283 ?ta03 ltc1283 0.1 m f 4.7 m f f cho ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd v in { to oscilloscope cd4520 clk en q1 q2 q3 q4 reset v ss clock in 500khz max 3v v cc aclk sclk d in d out cs ref + ref v agnd v dd reset q4 q3 q2 q1 en clk f/64
23 ltc1283 u s a o pp l ic at i ty p i ca l mnemonic description lda #$50 configuration data for spcr sta $0a load configuration data into $0a lda #$ff configuration data for port c ddr sta $06 load configuration data into port c ddr bset 0, $02 make sure cs is high jsr read C/+ dummy read configures ltc1283 for next read jsr read +/C read ch6 with respect to ch7 jsr read C/+ read ch7 with respect to ch6 jsr chk sign determines which reading has valid data, converts to 2s complement and stores in ram read C / +: lda #$3f load d in word for ltc1283 into acc jsr transfer read ltc1283 routine lda $60 load msbs from ltc1283 into acc sta $71 store msbs in $71 lda $61 load lsbs from ltc1283 into acc sta $72 store lsbs in $72 rts return read + / C: lda #$7f load d in word for ltc1283 into acc jsr transfer read ltc1283 routine lda $60 load msbs from ltc1283 into acc sta $73 store msbs in $73 lda $61 load lsbs from ltc1283 into acc sta $74 store lsbs in $74 rts return transfer: bclr 0, $02 cs goes low sta $0c load d in into spi. start transfer loop 1: tst $0b test status of spif bpl loop 1 loop to previous instruction if not done lda $0c load contents of spi data reg. into acc sta $0c start next cycle sta $60 store msbs in $60 mnemonic description loop 2: tst $0b test status of spif bpl loop 2 loop to previous instruction if not done bset 0, $02 cs goes high lda $0c load contents of spi data reg. into acc sta $61 store lsbs in $61 rts return chk sign: lda $73 load msbs of +/C read into acc ora $74 or acc (msbs) with lsbs of +/C read beq minus if result is 0 goto minus clc clear carry ror $73 rotate right $73 through carry ror $74 rotate right $74 through carry lda $73 load msbs of +/C read into acc sta $77 store msbs in ram location $77 lda $74 load lsbs of +/C read into acc sta $87 store lsbs in ram location $87 bra end goto end of routine minus: clc clear carry ror $71 shift msbs of C/+ read right ror $72 shift lsbs C/+ read right com $71 1s complement of msbs com $72 1s complement of lsbs lda $72 load lsbs into acc add #$01 add 1 to lsbs sta $72 store acc in $72 clra clear acc adc $71 add with carry to msbs. result in acc sta $71 store acc in $71 sta $77 store msbs in ram location $77 lda $72 load lsbs in acc sta $87 store lsbs in ram location $87 end: rts return sneak-a-bit code for the ltc1283 using the mc68hc05c4 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of circuits as described herein will not infringe on existing patent rights.
24 ltc1283 package descriptio u linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7487 (408) 432-1900 l fax : (408) 434-0507 l telex : 499-3977 lt/gp 0294 2k rev a ? printed in usa ? linear technology corporation 1994 n package 20-lead plastic dip sol20 0392 note: pin 1 ident, notch on top and cavities on the bottom of packages are the manufacturing options. the part may be supplied with or without any of the options. see note 0.496 ?0.512 (12.598 ?13.005) 20 19 18 17 16 15 14 13 1 23 4 5 6 78 0.394 ?0.419 (10.007 ?10.643) 910 11 12 0.037 ?0.045 (0.940 ?1.143) 0.004 ?0.012 (0.102 ?0.305) 0.093 ?0.104 (2.362 ?2.642) 0.050 (1.270) typ 0.014 ?0.019 (0.356 ?0.482) typ 0??8?typ see note 0.009 ?0.013 (0.229 ?0.330) 0.016 ?0.050 (0.406 ?1.270) 0.291 ?0.299 (7.391 ?7.595) 45 0.010 ?0.029 (0.254 ?0.737) 0.005 (0.127) rad min s package 20-lead plastic sol n20 0592 0.015 (0.381) min 0.125 (3.175) min 0.130 ?0.005 (3.302 ?0.127) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.018 ?0.003 (0.457 ?0.076) 0.065 ?0.015 (1.651 ?0.381) 0.100 ?0.010 (2.540 ?0.254) 0.260 ?0.010 (6.604 ?0.254) 1.040 (26.416) max 12 3 4 5 6 7 8 910 19 11 12 13 14 16 15 17 18 20 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.025 0.015 +0.635 0.381 8.255 () dimensions are in inches (millimeters) unless otherwise noted.

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